On 10/06/10 08:43 PM, Robert Hancock wrote: ..
My memory is fuzzy but I thought this came up before on PPC and I also thought the conclusion was that the platform code (for writel, etc.) should enforce ordering of MMIO accesses with respect to normal RAM accesses. (Or maybe it was just MMIO accesses with respect to each other?) I don't think the answer to that question has been clearly documented anywhere, which is somewhat unfortunate.
.. Different problem. That discussion was for PIO reads into the page cache, and ensuring coherency from all of that. Whereas this patch is just ordinary low-level chipset programming, and ensuring the descriptors are visible before issuing the "go" command. -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
