The driver's resetproc() method resets both channels at once -- most probably
by driving RESET- on them. Not only such reset can severely disturb concurrent
operations on another channel, it also ensues 2-second delay, while there's no
apparent reason why SRST reset being performed prior to resetproc() call needs
to be followed up by another reset.
Signed-off-by: Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx>
---
The patch is against the ide-2.6.git 'for-next' branch, atop of 2 patches
sent recently...
Now long removed driver code had something about downgrade from UDMA to MWDMA
not working without this reset trick but the kernel doesn't do such downgrade
anyway, it can only fall back from UDMA right to PIO, and anyway it's not clear
*how* it could have helped without touching the timing registers -- well, it
would have cleared the UDMA mode on the drive, and what?..
drivers/ide/pdc202xx_old.c | 17 -----------------
1 files changed, 17 deletions(-)
Index: ide-2.6/drivers/ide/pdc202xx_old.c
===================================================================
--- ide-2.6.orig/drivers/ide/pdc202xx_old.c
+++ ide-2.6/drivers/ide/pdc202xx_old.c
@@ -203,22 +203,6 @@ static int pdc202xx_dma_end(ide_drive_t
return ide_dma_end(drive);
}
-static void pdc202xx_reset(ide_drive_t *drive)
-{
- ide_hwif_t *hwif = drive->hwif;
- unsigned long high_16 = hwif->extra_base - 16;
- u8 udma_speed_flag = inb(high_16 | 0x001f);
-
- printk(KERN_WARNING "PDC202xx: software reset...\n");
-
- outb(udma_speed_flag | 0x10, high_16 | 0x001f);
- mdelay(100);
- outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
- mdelay(2000); /* 2 seconds ?! */
-
- ide_set_max_pio(drive);
-}
-
static int init_chipset_pdc202xx(struct pci_dev *dev)
{
unsigned long dmabase = pci_resource_start(dev, 4);
@@ -279,7 +263,6 @@ static const struct ide_port_ops pdc2026
.set_pio_mode = pdc202xx_set_pio_mode,
.set_dma_mode = pdc202xx_set_mode,
.quirkproc = pdc202xx_quirkproc,
- .resetproc = pdc202xx_reset,
.cable_detect = pdc2026x_cable_detect,
};
--
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