Martin Michlmayr wrote:
From: Saeed Bishara <saeed@xxxxxxxxxxx>
The old value (in clock cycles) is not suitable for soc devices that
have internal clock more that 150MHz.
Signed-off-by: Saeed Bishara <saeed@xxxxxxxxxxx>
Signed-off-by: Martin Michlmayr <tbm@xxxxxxxxxx>
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 5315b5f..f19f2e3 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -3330,7 +3330,7 @@ static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
ZERO(0x024); /* respq outp */
ZERO(0x020); /* respq inp */
ZERO(0x02c); /* test control */
- writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
+ writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
}
#undef ZERO
..
I want to see somebody actually test/verify that
this works with PIO/MWDMA2 devices (eg. CF cards) first.
Test results?
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