akpm@xxxxxxxxxxxxxxxxxxxx wrote:
From: Alan Cox <alan@xxxxxxxxxxxxxxxxxxx>
With 32bit PIO we can use the posted write buffers, but only for 32bit I/O
cycles. This means we must disable the FIFO for ATAPI where a final 16bit
cycle may occur.
Rework the FIFO logic so that we disable the FIFO then selectively
re-enable it when we set the timings on AMD devices. Also fix a case
where we scribbled on PCI config 0x41 of Nvidia chips when we shouldn't.
Signed-off-by: Alan Cox <alan@xxxxxxxxxxxxxxxxxxx>
Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>
Pinged Alan on 2/2, no response.
This seems necessary... but too instrusive and not yet well tested
enough for 2.6.29-rc?
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