Mikael Pettersson wrote:
Jeff Garzik writes:
> hrm.... at this point we have deviated massively from the standard
> Promise method of hard reset...
>
> * set PMP port
> * make hotplug irqs
> * reset port# in PDC_GLOBAL_CTL
> * pdc_reset_port()
> * reset FPDMA -- probably a good idea even if not doing FPDMA
> * clear SATA Error register (0xffffffff)
> * clear errors-reported-from-link-layer register
> * wait standard length of time for SATA connection
> * clear hotplug bits
> * set PMP port
>
> The PDC_GLOBAL_CTL bitbang is the most notable missing element in the
I assume you meant the PCI control register (offset 0x48).
> hard reset path, though we also miss clearing an apparently-important
> error register as well. FPDMA reset would be a good idea I think, even
> if not in use, mainly for paranoia's sake and because that's what
> Promise's driver does.
Here's a patch on top of 2.6.28-rc6 that should make sata_promise's
reset sequences a closer match to what Promise's drivers do.
- soft reset (pdc_reset_port):
* wait for ATA engine to not be in packet command mode (2nd gen only)
* write reset bit in PDC_CTLSTAT before the first read in the loop
* for 2nd gen SATA follow up with FPDMA reset and clearing error status registers
- hard reset (pdc_sata_hardreset):
* wait for ATA engine to not be in packet command mode (2nd gen only)
* reset ATA engine via the PCI control register
* Tejun's change to use non-waiting hardreset + follow-up SRST
I'm not changing the hotplug mask bits since they are taken care
of by sata_promise's ->freeze() and ->thaw() operations. And I'm
not writing the PMP port # because that's always zero (for now).
Tested here on a SATAII150 TX2plus w/ two sata disks, some hdparm -y
+ smartctl tests which used to cause timeouts on one of those disks,
and some parallel dd:s to stress things a little. No issues found.
I'll test it on a 1st gen 20378 next week.
Testers welcome.
Any updates?
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