Stanislaw Gruszka wrote:
Signed-off-by: Stanislaw Gruszka <stf_xl@xxxxx>
[...]
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index b753cb8..503651a 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c @@ -347,6 +347,103 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} #endif +/* -------------------------------------------------------------------- + * IDE + * -------------------------------------------------------------------- */ + +#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) + +/* Proper CS address space will be added */ +#define AT91_IDE_TASK_FILE 0x00c00000 +#define AT91_IDE_CTRL_REG 0x00e00000
Why are you assuming that these offsets are not board specifec I wonder? Theyu clearly depend on how the -CSx were wired on the board -- it's the same board specific data as your IRQ.
Are CPU specific.
Ah, sorry, I've missed that in the datasheet -- only looked into the SMC section and that's described in the EBI section...
Actually all AT91(except RM9200) use the same offsets, so could be moved from here to driver code, like in at91_cf driver. In this file only we will have proper Chip Select address space resource.
Then it indeed makes much sense having a single platfrom device for both IDE driver and the possible PCMCIA driver with a single memory resource covering the whole CS4/5 range as the drivers will know what subranges they want to use.
Cheers Stanislaw Gruszka
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