On Mon, Nov 24, 2008 at 7:38 AM, Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx> wrote: > Hello. > > Alan Cox wrote: > >>>> It's 240, not 242 ns as 33 is actually 33.333. > >>> The maximum values give cycle time of 480 ns menaing that the controller >>> doesn't support PIO mode 0. Hm... > >> Even if you clear the enable for the timing register ? > > These fast timing bits are documented as reserved. The spec says that PIO mode 0 is supported, but Sergei is correct -- the maximum values give a cycle time of 480 ns. How can this be? The old driver appeared to have tried to support PIO mode 0 by setting to the maximum. Which fast timing bits are documented as reserved? My spec has the IDE Drive 0/1 Recovery Time and IDE Drive 0/1 Pulse Width bits in it. Are there other timing bits that aren't documented in my spec? Please excuse my dumb question -- I'm a little over my head here. >> Alan > > MBR, Sergei Shane -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
