Hello.
Tejun Heo wrote:
The DMA_IRQ bit in the bmdma status register is always set when IDEIRQ
is asserted allowing spurious IRQ detection. Detect spurious IRQs and
clear them. This protects ata_piix against nobody-cared which gets
reported not so rarely.
This should be more generic, as several IDE controllers have the separate
IDE interrupt status bits.
Signed-off-by: Tejun Heo <tj@xxxxxxxxxx>
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 8e37be1..b438edc 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -922,6 +922,58 @@ static int piix_sidpr_scr_read(struct ata_link *link,
return 0;
}
+static irqreturn_t piix_interrupt(int irq, void *dev_instance)
+{
[...]
+ /*
+ * Control reaches here if HSM is not expecting IRQ.
+ * If the controller is actually asserting IRQ line,
+ * this will lead to nobody cared. Fortuantely,
+ * DMA_INTR of PIIX is set whenever IDEIRQ is set so
Frankly speaking, I'm not sure about the PIIX chips themselves... Is that
documented by Intel?
MBR, Sergei
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