Sergei Shtylyov wrote:
The DPLL tuning code always set up it for 66 MHz due to wrong UltraDMA mask including mode 5 used to check for the necessity of 66 MHz clocking -- this caused 66 MHz clock to be used for HPT374 chip that does not tolerate it. While fixing this, also remove PLL mode from the TODO list -- I don't think it's still a relevant item. Signed-off-by: Sergei Shtylyov <sshtylyov@xxxxxxxxxxxxx> --- This is against the current Linus tree -- with wording in the header fixed. :-) drivers/ata/pata_hpt37x.c | 12 ++++-------- 1 files changed, 4 insertions(+), 8 deletions(-)
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