Hello, I wrote:
I felt inspired by this explanation (thanks!) and took a look at hpt374-opensource-v2.10 vendor driver. Here is something interesting:
glbdata.c:
... #ifdef CLOCK_66MHZ ULONG setting370_66[] = { 0xd029d5e, 0xd029d26, 0xc829ca6, 0xc829c84, 0xc829c62, 0x2c829d2c, 0x2c829c66, 0x2c829c62, 0x1c829c62, 0x1c9a9c62, 0x1c929c62, 0x1c8e9c62, 0x1c8a9c62, 0x1c8a9c62/*0x1cae9c62*/, 0x1c869c62, 0x1c869c62, }; ...
hpt366.c:
... static u32 sixty_six_base_hpt37x[] = { /* XFER_UDMA_6 */ 0x1c869c62, /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ ...
So we are using Dual ATA Clock for UDMA5 whereas vendor driver doesn't
This is so in all other HPT drivers (and HPT371N datasheet has the same figures -- this chip is the only one supporting UDMA6 and having the default DPLL clock > 50 MHz).
What I meant to say was the only one I have a datasheet for. :-) MBR, Sergei - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
