> Hrm... so all MMIO drivers (PDC, etc...) are broken you think ? If they use the SRST and the chipset does more than tiny amounts of mmio posting then yes. > What would be the solution there ? A read to flush the posted write to > the control register would work in the middle of a soft reset ? If yes, > what register do you suggest we read ? Anything non taskfile, which is tricky to do arbitarily for all controllers - this is why I didn't just stuff in a simple fix and post it. For BMDMA controllers most of them have a load of other MMIO registers we can read (eg the SIL680 has the PRD table address you can read harmlessly), once we get beyond SFF BMDMA however it will be controller dependant and we probably have to actually specify what register is used for dummy posting reads when we set up the device. For I/O space we don't get posting so life is easy. Jeff ? Alan - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
