Mark Lord wrote:
Albert Lee wrote:
Jeff Garzik wrote:
Applied, though I think its an open question what happens with
CDB-interrupt ATAPI devices want to do DMA. Perhaps we just get an
interrupt event that we clear, then life proceeds as normal.
Oh yeah, from experience I know that the interrupt and DRQ bit
are *NOT* synchronized with these devices.. I believe that the IRQ
sometimes arrives early, and sometimes late.
Reading the ATA status reg after the IRQ always clears the IRQ,
and is usually necessary for the transfer to continue.
The last time I did a full ATAPI driver, it used both periodic polling
and an IRQ handler to wait for (DRQ && !BUSY).
Cheers
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