Albert Lee wrote:
Tejun Heo wrote:
For ATA PIO write transfers, the first transfer and n'th transfers
aren't really different. The code would be simpler if it handles the
first ATA PIO write in HSM_ST. And if we do that, HSM_ST_FIRST can be
renamed to HSM_ST_CDB. Hmmm.. Maybe this should be done in separate
series of patches.
For ATA PIO write transfer, the first transfer is different:
It is always done by polling, even if irq is turned on.
If we treat the first PIO write transfer as HSM_ST, we need to add some
additional logic to HSM_ST and check whether it is first transfer or not. If it is,
and irq is on, the transition from polling to interrupt-driven must be protected
by spinlock, similar to what's done in HSM_ST_FIRST.
Oh, you're right. I wasn't thinking of the spinlock. I implemented HSM
for sata_sil vdma (still slightly broken) and made its HSM function
always called under the host spinlock, so I could merge ATA HSM_ST_FIRST
into HSM_ST for ATA WRITE's and got confused about your HSM. :-)
Hmmm.. I'm not sure but I recall to read about IDE controllers reacting
badly when disturbed during PIO thus requiring irq-off during PIO. Does
anyone know better about this?
--
tejun
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