On 26.02.23 21:13, Geert Uytterhoeven wrote:
Hi David,
Hi Geert,
On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand <david@xxxxxxxxxx> wrote:Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit from the type. Generic MM currently only uses 5 bits for the type (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused. The shift by 2 when converting between PTE and arch-specific swap entry makes the swap PTE layout a little bit harder to decipher. While at it, drop the comment from paulus---copy-and-paste leftover from powerpc where we actually have _PAGE_HASHPTE---and mask the type in __swp_entry_to_pte() as well. Cc: Michal Simek <monstr@xxxxxxxxx> Signed-off-by: David Hildenbrand <david@xxxxxxxxxx>Thanks for your patch, which is now commit b5c88f21531c3457 ("microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE") in
Right, it went upstream, so we can only fixup.
arch/m68k/include/asm/mcf_pgtable.h | 4 +--What is this m68k change doing here? Sorry for not noticing this earlier.
Thanks for the late review, still valuable :)That hunk should have gone into the previous patch, looks like I messed that up when reworking.
Furthermore, several things below look strange to me...arch/microblaze/include/asm/pgtable.h | 45 +++++++++++++++++++++------ 2 files changed, 37 insertions(+), 12 deletions(-) diff --git a/arch/m68k/include/asm/mcf_pgtable.h b/arch/m68k/include/asm/mcf_pgtable.h index 3f8f4d0e66dd..e573d7b649f7 100644 --- a/arch/m68k/include/asm/mcf_pgtable.h +++ b/arch/m68k/include/asm/mcf_pgtable.h @@ -46,8 +46,8 @@ #define _CACHEMASK040 (~0x060) #define _PAGE_GLOBAL040 0x400 /* 68040 global bit, used for kva descs */ -/* We borrow bit 7 to store the exclusive marker in swap PTEs. */ -#define _PAGE_SWP_EXCLUSIVE 0x080 +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ +#define _PAGE_SWP_EXCLUSIVE CF_PAGE_NOCACHECF_PAGE_NOCACHE is 0x80, so this is still bit 7, thus the new comment is wrong?
You're right, it's still bit 7 (and we use LSB-0 bit numbering in that file). I'll send a fixup.
/* * Externally used page protection values. diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h index 42f5988e998b..7e3de54bf426 100644 --- a/arch/microblaze/include/asm/pgtable.h +++ b/arch/microblaze/include/asm/pgtable.h @@ -131,10 +131,10 @@ extern pte_t *va_to_pte(unsigned long address); * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB * miss handler. Bit 27 is PAGE_USER, thus selecting the correct * zone. - * - PRESENT *must* be in the bottom two bits because swap cache - * entries use the top 30 bits. Because 4xx doesn't support SMP - * anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 - * is cleared in the TLB miss handler before the TLB entry is loaded. + * - PRESENT *must* be in the bottom two bits because swap PTEs use the top + * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we + * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler + * before the TLB entry is loaded.So the PowerPC 4xx comment is still here?
I only dropped the comment above __swp_type(). I guess you mean that we could also drop the "Because 4xx doesn't support SMP anyway, M is irrelevant so we borrow it for PAGE_PRESENT." sentence, correct? Not sure about the "Bit 30 is cleared in the TLB miss handler" comment, if that can similarly be dropped.
* - All other bits of the PTE are loaded into TLBLO without * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for * software PTE bits. We actually use bits 21, 24, 25, and @@ -155,6 +155,9 @@ extern pte_t *va_to_pte(unsigned long address); #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ #define _PMD_PRESENT PAGE_MASK +/* We borrow bit 24 to store the exclusive marker in swap PTEs. */ +#define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY_PAGE_DIRTY is 0x80, so this is also bit 7, thus the new comment is wrong?
In the example, I use MSB-0 bit numbering (which I determined to be correct in microblaze context eventually, but I got confused a couple a times because it's very inconsistent). That should be MSB-0 bit 24.
Thanks! -- Thanks, David / dhildenb
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