Re: [PATCH v3 1/8] irqchip/mips-gic: Only register IPI domain when SMP is enabled
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- To: Serge Semin <fancer.lancer@xxxxxxxxx>
- Subject: Re: [PATCH v3 1/8] irqchip/mips-gic: Only register IPI domain when SMP is enabled
- From: Marc Zyngier <maz@xxxxxxxxxx>
- Date: Thu, 07 Jul 2022 09:22:26 +0100
- Cc: Samuel Holland <samuel@xxxxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, Andy Shevchenko <andy.shevchenko@xxxxxxxxx>, Bartosz Golaszewski <brgl@xxxxxxxx>, Bjorn Helgaas <bhelgaas@xxxxxxxxxx>, Boris Ostrovsky <boris.ostrovsky@xxxxxxxxxx>, Borislav Petkov <bp@xxxxxxxxx>, Broadcom internal kernel review list <bcm-kernel-feedback-list@xxxxxxxxxxxx>, Chris Zankel <chris@xxxxxxxxxx>, Colin Ian King <colin.king@xxxxxxxxx>, Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>, Dexuan Cui <decui@xxxxxxxxxxxxx>, Florian Fainelli <f.fainelli@xxxxxxxxx>, Guo Ren <guoren@xxxxxxxxxx>, "H. Peter Anvin" <hpa@xxxxxxxxx>, Haiyang Zhang <haiyangz@xxxxxxxxxxxxx>, Helge Deller <deller@xxxxxx>, Ingo Molnar <mingo@xxxxxxxxxx>, Ivan Kokshaysky <ink@xxxxxxxxxxxxxxxxxxxx>, "James E.J. Bottomley" <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Joerg Roedel <joro@xxxxxxxxxx>, Juergen Gross <jgross@xxxxxxxx>, Julia Lawall <Julia.Lawall@xxxxxxxx>, "K. Y. Srinivasan" <kys@xxxxxxxxxxxxx>, Kees Cook <keescook@xxxxxxxxxxxx>, Krzysztof Wilczyński <kw@xxxxxxxxx>, Linus Walleij <linus.walleij@xxxxxxxxxx>, Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx>, Mark Rutland <mark.rutland@xxxxxxx>, Matt Turner <mattst88@xxxxxxxxx>, Max Filippov <jcmvbkbc@xxxxxxxxx>, Maximilian Heyne <mheyne@xxxxxxxxx>, Oleksandr Tyshchenko <oleksandr_tyshchenko@xxxxxxxx>, Rich Felker <dalias@xxxxxxxx>, Richard Henderson <rth@xxxxxxxxxxxxxxx>, Rikard Falkeborn <rikard.falkeborn@xxxxxxxxx>, Rob Herring <robh@xxxxxxxxxx>, Russell King <linux@xxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Stephen Hemminger <sthemmin@xxxxxxxxxxxxx>, Sven Schnelle <svens@xxxxxxxxxxxxxx>, Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>, Wei Liu <wei.liu@xxxxxxxxxx>, Wei Xu <xuwei5@xxxxxxxxxxxxx>, Will Deacon <will@xxxxxxxxxx>, Yoshinori Sato <ysato@xxxxxxxxxxxxx>, iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx, iommu@xxxxxxxxxxxxxxx, linux-alpha@xxxxxxxxxxxxxxx, linux-arm-kernel@xxxxxxxxxxxxxxxxxxx, linux-hyperv@xxxxxxxxxxxxxxx, linux-ia64@xxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, linux-mips@xxxxxxxxxxxxxxx, linux-parisc@xxxxxxxxxxxxxxx, linux-pci@xxxxxxxxxxxxxxx, linux-sh@xxxxxxxxxxxxxxx, linux-xtensa@xxxxxxxxxxxxxxxx, x86@xxxxxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxxx, kernel test robot <lkp@xxxxxxxxx>
- In-reply-to: <20220705135243.ydbwfo4kois64elr@mobilestation>
- References: <20220701200056.46555-1-samuel@sholland.org> <20220701200056.46555-2-samuel@sholland.org> <20220705135243.ydbwfo4kois64elr@mobilestation>
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On Tue, 05 Jul 2022 14:52:43 +0100,
Serge Semin <fancer.lancer@xxxxxxxxx> wrote:
>
> Hi Samuel
>
> On Fri, Jul 01, 2022 at 03:00:49PM -0500, Samuel Holland wrote:
> > The MIPS GIC irqchip driver may be selected in a uniprocessor
> > configuration, but it unconditionally registers an IPI domain.
> >
> > Limit the part of the driver dealing with IPIs to only be compiled when
> > GENERIC_IRQ_IPI is enabled, which corresponds to an SMP configuration.
>
> Thanks for the patch. Some comment is below.
>
> >
> > Reported-by: kernel test robot <lkp@xxxxxxxxx>
> > Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
> > ---
> >
> > Changes in v3:
> > - New patch to fix build errors in uniprocessor MIPS configs
> >
> > drivers/irqchip/Kconfig | 3 +-
> > drivers/irqchip/irq-mips-gic.c | 80 +++++++++++++++++++++++-----------
> > 2 files changed, 56 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index 1f23a6be7d88..d26a4ff7c99f 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -322,7 +322,8 @@ config KEYSTONE_IRQ
> >
> > config MIPS_GIC
> > bool
> > - select GENERIC_IRQ_IPI
> > + select GENERIC_IRQ_IPI if SMP
>
> > + select IRQ_DOMAIN_HIERARCHY
>
> It seems to me that the IRQ domains hierarchy is supposed to be
> created only if IPI is required. At least that's what the MIPS GIC
> driver implies. Thus we can go further and CONFIG_IRQ_DOMAIN_HIERARCHY
> ifdef-out the gic_irq_domain_alloc() and gic_irq_domain_free()
> methods definition together with the initialization:
>
> static const struct irq_domain_ops gic_irq_domain_ops = {
> .xlate = gic_irq_domain_xlate,
> +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
> .alloc = gic_irq_domain_alloc,
> .free = gic_irq_domain_free,
> +#endif
> .map = gic_irq_domain_map,
> };
>
> If the GENERIC_IRQ_IPI config is enabled, CONFIG_IRQ_DOMAIN_HIERARCHY
> will be automatically selected (see the config definition in
> kernel/irq/Kconfig). If the IRQs hierarchy is needed for some another
> functionality like GENERIC_MSI_IRQ_DOMAIN or GPIOs then they will
> explicitly enable the IRQ_DOMAIN_HIERARCHY config thus activating the
> denoted .alloc and .free methods definitions.
>
> To sum up you can get rid of the IRQ_DOMAIN_HIERARCHY config
> force-select from this patch and make the MIPS GIC driver code a bit
> more coherent.
>
> @Marc, please correct me if were wrong.
Either way probably works correctly, but Samuel's approach is more
readable IMO. It is far easier to reason about a high-level feature
(GENERIC_IRQ_IPI) than an implementation detail (IRQ_DOMAIN_HIERARCHY).
If you really want to save a handful of bytes, you can make the
callbacks conditional on GENERIC_IRQ_IPI, and be done with it. But
this can come as an additional patch.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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