Re: [RFC v2 01/39] Kconfig: introduce HAS_IOPORT option and select it as necessary
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- To: "Maciej W. Rozycki" <macro@xxxxxxxxxxx>
- Subject: Re: [RFC v2 01/39] Kconfig: introduce HAS_IOPORT option and select it as necessary
- From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>
- Date: Fri, 6 May 2022 16:56:56 +0200
- Cc: David Laight <David.Laight@xxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxxxx>, Rich Felker <dalias@xxxxxxxx>, "open list:IA64 (Itanium) PLATFORM" <linux-ia64@xxxxxxxxxxxxxxx>, "open list:SUPERH" <linux-sh@xxxxxxxxxxxxxxx>, Catalin Marinas <catalin.marinas@xxxxxxx>, Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>, "open list:MIPS" <linux-mips@xxxxxxxxxxxxxxx>, "James E.J. Bottomley" <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx>, "open list:SPARC + UltraSPARC (sparc/sparc64)" <sparclinux@xxxxxxxxxxxxxxx>, "open list:RISC-V ARCHITECTURE" <linux-riscv@xxxxxxxxxxxxxxxxxxx>, Will Deacon <will@xxxxxxxxxx>, linux-arch <linux-arch@xxxxxxxxxxxxxxx>, Yoshinori Sato <ysato@xxxxxxxxxxxxx>, Helge Deller <deller@xxxxxx>, "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@xxxxxxxxxx>, Russell King <linux@xxxxxxxxxxxxxxx>, Ingo Molnar <mingo@xxxxxxxxxx>, linux-pci <linux-pci@xxxxxxxxxxxxxxx>, Bjorn Helgaas <helgaas@xxxxxxxxxx>, Matt Turner <mattst88@xxxxxxxxx>, Albert Ou <aou@xxxxxxxxxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxx>, Niklas Schnelle <schnelle@xxxxxxxxxxxxx>, "open list:M68K ARCHITECTURE" <linux-m68k@xxxxxxxxxxxxxxx>, Ivan Kokshaysky <ink@xxxxxxxxxxxxxxxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, "moderated list:ARM PORT" <linux-arm-kernel@xxxxxxxxxxxxxxxxxxx>, Richard Henderson <rth@xxxxxxxxxxxxxxx>, Michal Simek <monstr@xxxxxxxxx>, Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>, "open list:PARISC ARCHITECTURE" <linux-parisc@xxxxxxxxxxxxxxx>, Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, Linux Kernel Mailing List <linux-kernel@xxxxxxxxxxxxxxx>, Palmer Dabbelt <palmer@xxxxxxxxxxx>, "open list:ALPHA PORT" <linux-alpha@xxxxxxxxxxxxxxx>, Borislav Petkov <bp@xxxxxxxxx>, "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" <linuxppc-dev@xxxxxxxxxxxxxxxx>, "David S. Miller" <davem@xxxxxxxxxxxxx>
- In-reply-to: <alpine.DEB.2.21.2205061440260.52331@angie.orcam.me.uk>
- References: <CAK8P3a0sJgMSpZB_Butx2gO0hapYZy-Dm_QH-hG5rOaq_ZgsXg@mail.gmail.com> <20220505161028.GA492600@bhelgaas> <CAK8P3a3fmPExr70+fVb564hZdGAuPtYa-QxgMMe5KLpnY_sTrQ@mail.gmail.com> <alpine.DEB.2.21.2205061058540.52331@angie.orcam.me.uk> <CAK8P3a0NzG=3tDLCdPj2=A__2r_+xiiUTW=WJCBNp29x_A63Og@mail.gmail.com> <alpine.DEB.2.21.2205061314110.52331@angie.orcam.me.uk> <5239892986c94239a122ab2f7a18a7a5@AcuMS.aculab.com> <alpine.DEB.2.21.2205061412080.52331@angie.orcam.me.uk> <3669a28a055344a792b51439c953fd30@AcuMS.aculab.com> <alpine.DEB.2.21.2205061440260.52331@angie.orcam.me.uk>
Hi Maciej,
On Fri, May 6, 2022 at 4:44 PM Maciej W. Rozycki <macro@xxxxxxxxxxx> wrote:
> On Fri, 6 May 2022, David Laight wrote:
> > > It was retrofitted in that x86 systems already existed for ~15 years when
> > > PCI came into picture. Therefore the makers of the CPU ISA couldn't have
> > > envisaged the need for config access instructions like they did for memory
> > > and port access.
> >
> > Rev 2.0 of the PCI spec (1993) defines two mechanisms for config cycles.
> > #2 is probably the first one and maps all of PCI config space into
> > 4k of IO space (PCI bridges aren't supported).
>
> This one is even more horrid than #1 in that it requires two separate
> preparatory I/O writes rather than just one, one to the Forward Register
> (at 0xcfa) to set the bus number, and another to the Configuration Space
> Enable Register (at 0xcf8) to set the function number, before you can
> issue a configuration read or write to a device. So you need MP locking
> too.
>
> NB only peer bridges aren't supported with this mechanism, normal PCI-PCI
> bridges are, via the Forward Register.
>
> > #1 requires a pair of accesses (and SMP locking).
> >
> > Neither is really horrid.
>
> Both are. First neither is MP-safe and second both are indirect in that
> you need to poke at some chipset registers before you can issue the actual
> read or write.
>
> Sane access would require a single CPU instruction to read or write from
> the configuration space. To access the conventional PCI configuration
> space in a direct linear manner you need 256 * 21 * 8 * 256 = 10.5MiB of
> address space. Such amount of address space seems affordable even with
> 32-bit systems.
Won't have fit in the legacy 1 MiB space ("640 KiB...").
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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