Re: [RFC v2 01/39] Kconfig: introduce HAS_IOPORT option and select it as necessary
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- To: "Maciej W. Rozycki" <macro@xxxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxxxx>
- Subject: Re: [RFC v2 01/39] Kconfig: introduce HAS_IOPORT option and select it as necessary
- From: Niklas Schnelle <schnelle@xxxxxxxxxxxxx>
- Date: Fri, 06 May 2022 14:55:52 +0200
- Cc: Bjorn Helgaas <helgaas@xxxxxxxxxx>, Arnd Bergmann <arnd@xxxxxxxx>, Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, Linux Kernel Mailing List <linux-kernel@xxxxxxxxxxxxxxx>, linux-arch <linux-arch@xxxxxxxxxxxxxxx>, linux-pci <linux-pci@xxxxxxxxxxxxxxx>, Richard Henderson <rth@xxxxxxxxxxxxxxx>, Ivan Kokshaysky <ink@xxxxxxxxxxxxxxxxxxxx>, Matt Turner <mattst88@xxxxxxxxx>, Russell King <linux@xxxxxxxxxxxxxxx>, Catalin Marinas <catalin.marinas@xxxxxxx>, Will Deacon <will@xxxxxxxxxx>, Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>, Michal Simek <monstr@xxxxxxxxx>, Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>, "James E.J. Bottomley" <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx>, Helge Deller <deller@xxxxxx>, Michael Ellerman <mpe@xxxxxxxxxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, Palmer Dabbelt <palmer@xxxxxxxxxxx>, Albert Ou <aou@xxxxxxxxxxxxxxxxx>, Yoshinori Sato <ysato@xxxxxxxxxxxxx>, Rich Felker <dalias@xxxxxxxx>, "David S. Miller" <davem@xxxxxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, Ingo Molnar <mingo@xxxxxxxxxx>, Borislav Petkov <bp@xxxxxxxxx>, Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>, "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@xxxxxxxxxx>, "open list:ALPHA PORT" <linux-alpha@xxxxxxxxxxxxxxx>, "moderated list:ARM PORT" <linux-arm-kernel@xxxxxxxxxxxxxxxxxxx>, "open list:IA64 (Itanium) PLATFORM" <linux-ia64@xxxxxxxxxxxxxxx>, "open list:M68K ARCHITECTURE" <linux-m68k@xxxxxxxxxxxxxxx>, "open list:MIPS" <linux-mips@xxxxxxxxxxxxxxx>, "open list:PARISC ARCHITECTURE" <linux-parisc@xxxxxxxxxxxxxxx>, "open list:LINUX FOR POWERPC (32-BIT AND 64-BIT)" <linuxppc-dev@xxxxxxxxxxxxxxxx>, "open list:RISC-V ARCHITECTURE" <linux-riscv@xxxxxxxxxxxxxxxxxxx>, "open list:SUPERH" <linux-sh@xxxxxxxxxxxxxxx>, "open list:SPARC + UltraSPARC (sparc/sparc64)" <sparclinux@xxxxxxxxxxxxxxx>
- In-reply-to: <alpine.DEB.2.21.2205061314110.52331@angie.orcam.me.uk>
- References: <CAK8P3a0sJgMSpZB_Butx2gO0hapYZy-Dm_QH-hG5rOaq_ZgsXg@mail.gmail.com> <20220505161028.GA492600@bhelgaas> <CAK8P3a3fmPExr70+fVb564hZdGAuPtYa-QxgMMe5KLpnY_sTrQ@mail.gmail.com> <alpine.DEB.2.21.2205061058540.52331@angie.orcam.me.uk> <CAK8P3a0NzG=3tDLCdPj2=A__2r_+xiiUTW=WJCBNp29x_A63Og@mail.gmail.com> <alpine.DEB.2.21.2205061314110.52331@angie.orcam.me.uk>
On Fri, 2022-05-06 at 13:27 +0100, Maciej W. Rozycki wrote:
> On Fri, 6 May 2022, Arnd Bergmann wrote:
>
> > > If this is PCI/PCIe indeed, then an I/O access is just a different bit
> > > pattern put on the bus/in the TLP in the address phase. So what is there
> > > inherent to the s390 architecture that prevents that different bit pattern
> > > from being used?
> >
> > The hardware design for PCI on s390 is very different from any other
> > architecture, and more abstract. Rather than implementing MMIO register
> > access as pointer dereference, this is a separate CPU instruction that
> > takes a device/bar plus offset as arguments rather than a pointer, and
> > Linux encodes this back into a fake __iomem token.
>
> OK, that seems to me like a reasonable and quite a clean design (on the
> hardware side).
>
> So what happens if the instruction is given an I/O rather than memory BAR
> as the relevant argument? Is the address space indicator bit (bit #0)
> simply ignored or what?
See my answer to Arnd for some more background but there simply isn't a
way to formulate an I/O access. In the old style PCI instructions the
BAR number and the function handle are put in a register before the
access. BAR number 15 is used to access config space. If there is no
BAR for that number the instruction fails with a non-zero CC.
>
> > > But that has nothing to do with the presence or absence of any specific
> > > processor instructions. It's just a limitation of bus glue. So I guess
> > > it's just that all PCI/PCIe glue logic implementations for s390 have such
> > > a limitation, right?
> >
> > There are separate instructions for PCI memory and config space, but
> > no instructions for I/O space, or for non-PCI MMIO that it could be mapped
> > into.
>
> The PCI configuration space was retrofitted into x86 systems (and is
> accessed in an awkward manner with them), but with a new design such a
> clean approach is most welcome IMHO. Thank you for your explanation.
>
> Maciej
Well our design is a retrofit too considering s390x is a direct
decendent of IBM System/360 which one could argue to have been the
first ISA. But yes as PCI support was only added with PCIe and with a
machine level hypervisor already in place we do get shielded a lot from
the gritty details.
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