Re: bit fields && data tearing
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- To: James Bottomley <James.Bottomley@xxxxxxxxxxxxxxxxxxxxx>, Peter Hurley <peter@xxxxxxxxxxxxxxxxxx>
- Subject: Re: bit fields && data tearing
- From: "H. Peter Anvin" <hpa@xxxxxxxxx>
- Date: Mon, 08 Sep 2014 20:20:49 -0700
- Cc: paulmck@xxxxxxxxxxxxxxxxxx, One Thousand Gnomes <gnomes@xxxxxxxxxxxxxxxxxxx>, Jakub Jelinek <jakub@xxxxxxxxxx>, Mikael Pettersson <mikpelinux@xxxxxxxxx>, Benjamin Herrenschmidt <benh@xxxxxxxxxxxxxxxxxxx>, Richard Henderson <rth@xxxxxxxxxxx>, Oleg Nesterov <oleg@xxxxxxxxxx>, Miroslav Franc <mfranc@xxxxxxxxxx>, Paul Mackerras <paulus@xxxxxxxxx>, linuxppc-dev@xxxxxxxxxxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, linux-arch@xxxxxxxxxxxxxxx, Tony Luck <tony.luck@xxxxxxxxx>, linux-ia64@xxxxxxxxxxxxxxx
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On 09/08/2014 07:56 PM, James Bottomley wrote:
>>
>> Yeah, the extra requirement I added is basically nonsense, since the
>> only issue is what instructions the compiler is emitting. So if compiler
>> thinks the alignment is natural and combines the writes -- ok. If the
>> compiler thinks the alignment is off and doesn't combine the writes --
>> also ok.
>
> Yes, I think I can agree that the only real problem is gcc thinking the
> store or load needs splitting.
>
That seems much saner, and yes, that applies to any architecture which
needs unaligned references. Now, if the references are *actually*
unaligned they can end up being split even on x86, especially if they
cross cache line boundaries.
-hpa
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