> When handling Interrupt Source Override in MADT table, the default > ISA IRQ trigger model and poliarity should be edge-rising. > Current IA64 implmentation doesn't follow the specification and > set default ISA IRQ trigger model as level-low. With that wrong > configuration and when system runs out of interrupt vectors, > it will cause vector sharing among edge triggered ISA IRQ and > level triggered PCI IRQ, then interrupt storm. So change the code > to follow the specification. I chased the reference in ACPI to the MPS spec: http://www.intel.com/design/pentium/datashts/24201606.pdf Which says in table 4-10 "for example. EISA is active-low for level triggered interrupt" and "for example, EISA is edge-triggered". It looks to me that if MADT says "high", we should set high, if it says "low" we should set low. Ditto for trigger vs. level. But if we see the value "0" - then we have more work to do to determine what the bus we are on uses for its default. Did you find some other specification that gives a better explanation? Or did I miss something - can we only get to this routine for ISA? You've tested this patch - and it works for you - but is there a risk that it will break someone else? -Tony -- To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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