RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part
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- To: "Yu, Fenghua" <fenghua.yu@xxxxxxxxx>
- Subject: RE: [PATCH 2/2]Add Variable Page Size and IA64 Support in Intel IOMMU: IA64 Specific Part
- From: David Woodhouse <dwmw2@xxxxxxxxxxxxx>
- Date: Sat, 04 Oct 2008 07:09:57 +0100
- Cc: Bjorn Helgaas <bjorn.helgaas@xxxxxx>, "Luck, Tony" <tony.luck@xxxxxxxxx>, Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>, Ingo Molnar <mingo@xxxxxxx>, Avi Kivity <avi@xxxxxxxxxx>, Stephen Rothwell <sfr@xxxxxxxxxxxxxxxx>, Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx>, LKML <linux-kernel@xxxxxxxxxxxxxxx>, "linux-ia64@xxxxxxxxxxxxxxx" <linux-ia64@xxxxxxxxxxxxxxx>
- In-reply-to: <A6AD88C3F2289247BE726C37303E1EB8844A6398@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
- List-id: <linux-ia64.vger.kernel.org>
- References: <20081001165750.GA21272@xxxxxxxxxxxxxxxxxxxxx> <200810020951.08408.bjorn.helgaas@xxxxxx> <A6AD88C3F2289247BE726C37303E1EB88408AA3E@xxxxxxxxxxxxxxxxxxxxxxxxxxxx> <200810030941.42800.bjorn.helgaas@xxxxxx> <A6AD88C3F2289247BE726C37303E1EB8844A6398@xxxxxxxxxxxxxxxxxxxxxxxxxxxx>
On Fri, 2008-10-03 at 17:53 -0700, Yu, Fenghua wrote:
> >Architecturally, I'm surprised that ia64 would need to actually do a
> >cache flush. I would think the VT-d hardware would do coherent
> accesses which would make the cache flush unnecessary.
>
> VT-d hardware supports both non cache coherency and cache coherency by
> bit Coherency in Extended Capabilities Register.
But is the version without the cache coherency actually going to be
_seen_ on IA64?
> Could you please point me to the doc that explicitly says that
> architecturally ia64 doesn't need cache flush?
For safety, we can always make the driver just refuse to initialise on
IA64 if the cache coherency bit isn't set.
--
David Woodhouse Open Source Technology Centre
David.Woodhouse@xxxxxxxxx Intel Corporation
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