>> --- a/drivers/pci/dmar.c >> +++ b/drivers/pci/dmar.c >> @@ -35,6 +35,10 @@ >> #undef PREFIX >> #define PREFIX "DMAR:" >> >> +#ifdef CONFIG_IA64 >> +#define cpu_has_x2apic 0 >> +#endif > >hm, that's not too nice - why not add it to arch/ia64/include/? OK. I'll move this to arch/ia64/include (along with other #ifdef CONFIG_IA64 places if needed). >> diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h >> index e7b196b..d84612a 100644 >> --- a/include/linux/intel-iommu.h >> +++ b/include/linux/intel-iommu.h >> @@ -67,6 +67,13 @@ >> hi = readl(dmar + reg + 4); \ >> (((u64) hi) << 32) + lo; }) >> */ >> +#ifdef CONFIG_IA64 >> +#define dmar_readq readq >> +static inline void dmar_writeq(void __iomem *addr, u64 val) >> +{ >> + writeq(val, addr); >> +} >> +#else >> static inline u64 dmar_readq(void __iomem *addr) >> { >> u32 lo, hi; >> @@ -80,6 +87,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) >> writel((u32)val, addr); >> writel((u32)(val >> 32), addr + 4); >> } >> +#endif > >What's this all about? Why do we need #ifdef CONFIG_IA64 here? >Doesn't x86 provide its own readq/writeq implementation? This is a comment from Bjorn. In my patch, one readq/one writeq are working faster than two readl/two writel on IA64. X86 uses two readl/two writel so that the code works on both x86 and x86-64 although Intel IOMMU only has x86-64 version currently. dmar_readq() and dmar_writeq() are in moderate performance critical path. Do you think my current implementation is ok to have #ifdef CONFIG_IA64 here? Or I can change X86 to use readq/writeq as well or IA64 uses two readl/two writel for clean code? Thanks. -Fenghua -- To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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