Hi, Xiantao
>+void thash_vhpt_insert(VCPU *v, u64 pte, u64 itir, u64 va, int type)
>+{
>+ u64 phy_pte, psr;
>+ ia64_rr mrr;
>+
>+ mrr.val = ia64_get_rr(va);
>+ phy_pte = translate_phy_pte(&pte, itir, va);
>+
>+ if (itir_ps(itir) >= mrr.ps) {
>+ vhpt_insert(phy_pte, itir, va, pte);
>+ } else {
>+ phy_pte &= ~PAGE_FLAGS_RV_MASK;
>+ psr = ia64_clear_ic();
>+ ia64_itc(type, va, phy_pte, itir_ps(itir));
>+ ia64_set_psr(psr);
>+ ia64_srlz_i();
>+ }
>+}
You add ia64_srlz_i() into ia64_set_psr() with [02]patch.
So is this a redundancy if the patch is applied?
>+ */
>+int thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa, int
>type)
>+{
>+ u64 ps;
>+ u64 phy_pte;
>+ ia64_rr vrr, mrr;
>+ int ret = 0;
>+
>+ ps = itir_ps(itir);
>+ vrr.val = vcpu_get_rr(v, ifa);
>+ mrr.val = ia64_get_rr(ifa);
>+
>+ phy_pte = translate_phy_pte(&pte, itir, ifa);
>+
>+ /* Ensure WB attribute if pte is related to a normal mem page,
>+ * which is required by vga acceleration since qemu maps shared
>+ * vram buffer with WB.
>+ */
>+ if (!(pte & VTLB_PTE_IO) && ((pte & _PAGE_MA_MASK) !=
>_PAGE_MA_NAT)) {
>+ pte &= ~_PAGE_MA_MASK;
>+ phy_pte &= ~_PAGE_MA_MASK;
>+ }
>+
>+ if (pte & VTLB_PTE_IO)
>+ ret = 1;
>+
>+ vtlb_purge(v, ifa, ps);
>+ vhpt_purge(v, ifa, ps);
>+
>+ if (ps == mrr.ps) {
>+ if (!(pte&VTLB_PTE_IO)) {
>+ vhpt_insert(phy_pte, itir, ifa, pte);
>+ } else {
>+ vtlb_insert(v, pte, itir, ifa);
>+ vcpu_quick_region_set(VMX(v, tc_regions), ifa);
>+ }
>+ } else if (ps > mrr.ps) {
>+ vtlb_insert(v, pte, itir, ifa);
>+ vcpu_quick_region_set(VMX(v, tc_regions), ifa);
>+ if (!(pte&VTLB_PTE_IO))
>+ vhpt_insert(phy_pte, itir, ifa, pte);
>+ } else {
>+ u64 psr;
>+ phy_pte &= ~PAGE_FLAGS_RV_MASK;
>+ psr = ia64_clear_ic();
>+ ia64_itc(type, ifa, phy_pte, ps);
>+ ia64_set_psr(psr);
>+ ia64_srlz_i();
>+ }
>+
>+ return ret;
>+}
ditto
Best Regards,
Akio Takebe
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