On Tue, Oct 16, 2007 at 06:34:14PM +1000, Matthew Chapman wrote:
> Where would I find documentation on the Itanium 2 specific flags to
> PAL_PROC_SET_FEATURES?
"Intel® Itanium® 2 Processors Firmware Guide", though I don't see it
on the Intel website. Don't recall if the document is restricted.
> Linux arch/ia64/kernel/setup.c seems to enable bit 0x80, but there is no
> explanatory comment attached.
I assume you are refering to this code.
--------------------------------------
#ifdef CONFIG_MCKINLEY
{
# define FEATURE_SET 16
struct ia64_pal_retval iprv;
if (cpu_info->family == 0x1f) {
PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
(iprv.v1 | 0x80), FEATURE_SET, 0);
}
}
#endif
--------------------------------------
Note that it is setting bit 7 (0x80) in feature set 16 (not feature set 0).
> The Itanium 2 microarchitecture manual [1] says that early deferral of
> speculative memory ops (bypassing VHPT walker) can be enabled via
> PAL_PROC_SET_FEATURES, but as far as I can see does not specify anywhere
> which is the appropriate bit...
>
> Also, is it true that early deferral only happens with psr.ic=0, as
> per Table 5-2? What is the motivation for that?
>
> Matt
>
> [1] i.e. http://download.intel.com/design/Itanium2/manuals/25111003.pdf
>
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--
Russ Anderson RAS group SGI rja@xxxxxxx
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