On 9/4/07, Luck, Tony <tony.luck@xxxxxxxxx> wrote: > >> global cache purge in their chipset implementation. (For such cases, Intel provided a SAL > >> table entry to specify if ptc.g is allowed and how many). > > > > This seems odd. You never use that sal call to initialized noptcg. > > Is that an oversight? > > The mechanism is a SAL table entry, not a SAL call. Currently that > entry provides no mechanism to specify that ptc.g should not be used > at all (the entry provides the count of how many ptc.g can happen in > parallel, but the spec says that the value "0" means "1" :-( ) > > There is an ongoing discussion with DIG64 to use a currently reserved > field in the table to specify the value "0". If that change is approved, > then we can add code to enable Natalie's code based on the SAL table. > > -Tony > Yes, as Tony said this is a provision for the (near) future when the actual mechanism of how the ptc.g availability to be shown in the bios will be decided on. Then the boot option will be removed. The code is already urgently needed for current platform work by aforementioned companies :) Jes, thank - I will go through your remarks thoroughly, yours and Robin's, and will fight the wrapping thing to the end... Regards, --Natalie - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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