On Thu, 2007-08-02 at 14:56 -0700, Luck, Tony wrote: > > So I suspect at this stage that the race isn't affecting you. However, > > it looks to me that you put the burden on the fairly hot TLB miss path > > rather than on the much less hot invalidation path itself... > > Suggestions on how to do move the burden gratefully received. I don't > think that it is all that bad though. The re-read of the PGD>PUD>PMD>PTE > should all hit in the L1-D cache, which has single cycle latency. Allright. I'll look into it. Other archs have a similar issues and don't currently fix it. The easy fix for archs that have IPIs for TLB flushes is to batch the freeing of page tables pages. That's made a bit harder by the quicklist but I may just end up adding support for those to the mmu_gather. Ben. - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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