"Luck, Tony" wrote: > > Can you explain this part of the patch? > > -#define PCI32_ATE_CO (0x1 << 1) > -#define PCI32_ATE_PREC (0x1 << 2) > +#define PCI32_ATE_CO (0x1 << 1) /* PIC ASIC ONLY */ > +#define PCI32_ATE_PIO (0x1 << 1) /* TIOCP ASIC ONLY */ > > Why is PCI32_ATE_PIO now the same value as PCI_ATE_CO? The ATE (Address Translation Entry for 32bit PCI mappings) Attribute bits are different for our PIC Bridge ASIC and our TIOCP Bridge ASIC. On our PIC Bridge ASIC bit#1 is the `Coherent Translation' attribute, but on our TIOCP Bridge ASIC bit#1 is the `PIO' attribute -mike - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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