Mao, Bibo wrote on Thursday, November 02, 2006 1:06 AM > Chen, Kenneth W wrote: > > Mao, Bibo wrote on Wednesday, November 01, 2006 11:53 PM > >> else means that current cpu does not support 16 byte atomic operation. > >> If kprobe address is on slot 0/2, then memcpy still can execute. > > > > Do you allow kprobe insertion on "L+X" instruction? It looks like so. > > Then how do you maintain atomic update to L and X instruction right > > now with memcpy? > > From the code, It allows kprobes insertion on "L+X" instruction, and put > BREAK code on the slot 2. IA64 manual says that "the X slot may encode > break.i and nop.i in addition to any X-unit instruction". > It seems that for MLX, BREAK opcode should insert the higher 8 bytes firstly. That's exactly what I'm saying in the 2nd paragraph. > > "atomic update" is not really the exact word I want to use here. Don't > > you want to write the upper 8-byte first so that break opcode is jammed > > in there before updating the remaining 41-bit immediate value? Otherwise, > > writing lower 8-byte first will end up with a small window that original > > opcode seeing corrupted immediate value. And same logic extends to inserting probe on slot 1 instruction. The key is to jam in break opcode, before updating the remaining unused immediate value. - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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