Re: Synchronizing Bit operations V2
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- To: Andi Kleen <ak@xxxxxxx>
- Subject: Re: Synchronizing Bit operations V2
- From: Christoph Lameter <clameter@xxxxxxx>
- Date: Fri, 31 Mar 2006 09:45:18 -0800 (PST)
- Cc: Zoltan Menyhart <Zoltan.Menyhart@xxxxxxxx>, "Boehm, Hans" <hans.boehm@xxxxxx>, "Grundler, Grant G" <grant.grundler@xxxxxx>, "Chen, Kenneth W" <kenneth.w.chen@xxxxxxxxx>, akpm@xxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, linux-ia64@xxxxxxxxxxxxxxx
- In-reply-to: <p73vetu921a.fsf@xxxxxxxxxxxxx>
- References: <Pine.LNX.4.64.0603301300430.1014@xxxxxxxxxxxxxxxxxxxxxxxxx> <Pine.LNX.4.64.0603301615540.2023@xxxxxxxxxxxxxxxxxxxxxxxxx> <p73vetu921a.fsf@xxxxxxxxxxxxx>
On Fri, 31 Mar 2006, Andi Kleen wrote:
> Christoph Lameter <clameter@xxxxxxx> writes:
> > MODE_BARRIER
> > An atomic operation that is guaranteed to occur between
> > previous and later memory operations.
> I think it's a bad idea to create such an complicated interface.
> The chances that an average kernel coder will get these right are
> quite small. And it will be 100% untested outside IA64 I guess
> and thus likely be always slightly buggy as kernel code continues
> to change.
Powerpc can do similar things AFAIK. Not sure what other arches have
finer grained control over barriers but it could cover a lot of special
cases for other processors as well.
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