RE: Synchronizing Bit operations V2
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- To: "Chen, Kenneth W" <kenneth.w.chen@xxxxxxxxx>
- Subject: RE: Synchronizing Bit operations V2
- From: Christoph Lameter <clameter@xxxxxxx>
- Date: Thu, 30 Mar 2006 18:55:47 -0800 (PST)
- Cc: "'Nick Piggin'" <nickpiggin@xxxxxxxxxxxx>, "'Zoltan Menyhart'" <Zoltan.Menyhart@xxxxxxxx>, "'Boehm, Hans'" <hans.boehm@xxxxxx>, "'Grundler, Grant G'" <grant.grundler@xxxxxx>, akpm@xxxxxxxx, linux-kernel@xxxxxxxxxxxxxxx, linux-ia64@xxxxxxxxxxxxxxx
- In-reply-to: <200603310250.k2V2ofg28252@xxxxxxxxxxxxxxxxxxxx>
- References: <200603310250.k2V2ofg28252@xxxxxxxxxxxxxxxxxxxx>
On Thu, 30 Mar 2006, Chen, Kenneth W wrote:
> By the way, this is the same thing on x86: look at include/asm-i386/bitops.h:
>
> #define smp_mb__before_clear_bit() barrier()
> #define smp_mb__after_clear_bit() barrier()
>
> A simple compiler barrier, nothing but
> #define barrier() __asm__ __volatile__("": : :"memory")
>
> See, no memory ordering there, because clear_bit already has a LOCK prefix.
And that implies barrier behavior right?
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