[Trimmed linux-kernel, since this is IA64 specific.] > From: Christoph Lameter > The question is what does fence imply for the order of the > atomic operation. Will the operation be performed before or > after the barrier? > Or do we need barriers on both sides? I would assume so. > > If so then we may simulate that with a release and then do a > acquire load afterwards > > cmpxchg_rel(m, old, new); > return *m; /* m volatile so it has acquire semantics */ Is this really what you intended? The cmpxchg and the read of *m are not atomic. Operations in other threads may intervene. After looking at the spec again, I am convinced that it enforces ordering. But I'm not sure that helps. I would guess that just adding an mf at the end will give you at least similar performance. Hans - : send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
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