On Thu, Mar 30, 2006 at 08:43:43AM -0700, David Mosberger-Tang wrote: > On 3/30/06, Jack Steiner <steiner@xxxxxxx> wrote: > > > Is this problem unique to SN systems > > No, the same will happen on all other systems (that I know of). > > > The BIOS reports that most > > memory ranges support both CACHED & UNCACHED references. I _think_ > > this is correct. > > That's correct. The map shows the ways the page *can* be mapped, not > the way it *should* be mapped. > > It's strange that ACPI would prefer to use WC when WB mapping is > possible. They definitely need to pick one way and stick with it > though. As you say, mapping the same page with different cacheability > is a no-no (and at least in theory, it should cause an MCA even on > real hardware). It does, at least on our chipset. If the chipset detects a simultaneous UC & C reference, it generates a BUS error. It is surprising how quickly this MCA occurs when we break the rules. > > --david > > -- > Mosberger Consulting LLC, http://www.mosberger-consulting.com/ -- Jack - : send the line "unsubscribe linux-ia64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
|