> Thanks. But isn't it possible to attach an interrupt handler to SCL > GPIO? Or do you mean that the latency for IRQ handling is too high? Way too high for most systems. I made the in-kernel sloppy GPIO logic analyzer. From that experience, even with constant polling using an isolated CPU core, you would need at least a dedicatded 300MHz core to monitor 100kHz. With interrupts, it will probably be a magnitutde more. I scrapped that idea for the above analyzer, too slow.
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