Hi Carlos, On Fri, Dec 27, 2024 at 03:28:57PM +0800, Carlos Song wrote: > LPI2C support master controller and target controller enabled > simultaneously. Both controllers share the same SDA/SCL lines > and interrupt source but has a separate control and status > registers. When target is enabled and an interrupt has been > triggered, target register status will be checked to determine > IRQ source. Then enter the corresponding interrupt handler > function of master or target to handle the interrupt event. > > This patch supports basic target data read/write operations in > 7-bit target address. LPI2C target mode can be enabled by using > I2C slave backend. I2C slave backend behaves like a standard I2C > client. For simple use and test, Linux I2C slave EEPROM backend > can be used. > > Signed-off-by: Carlos Song <carlos.song@xxxxxxx> merged to i2c/i2c-host. Thanks, Andi
