In commit 35eba185fd1a ("i2c: designware: Calculate SCL timing
parameters for High Speed Mode") hs_hcnt and hs_lcnt are computed based
on fixed tHIGH = 160 and tLOW = 320. However, this fixed values only
applies to the combination of hardware parameters "IC_CAP_LOADING = 400pF"
and "IC_FREQ_OPTIMIZATION = 1". Outside of this combination, SCL frequency
may not reach 3.4 MHz if hs_hcnt and hs_lcnt are both computed using these
two fixed values.
Since there are no any registers controlling these two hardware
parameters, their values can only be noted through the device tree.
Michael Wu (2):
i2c: designware: determine HS tHIGH and tLOW based on HW paramters
dt-bindings: i2c: snps,designware-i2c: add bus-loading and
clk-freq-optimized
.../bindings/i2c/snps,designware-i2c.yaml | 19 +++++++++++++++
drivers/i2c/busses/i2c-designware-common.c | 16 +++++++++++++
drivers/i2c/busses/i2c-designware-core.h | 8 +++++++
drivers/i2c/busses/i2c-designware-master.c | 24 +++++++++++++++++--
drivers/i2c/busses/i2c-designware-platdrv.c | 2 ++
5 files changed, 67 insertions(+), 2 deletions(-)
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2.43.0
