Hi, kernel test robot noticed the following build warnings: [auto build test WARNING on andi-shyti/i2c/i2c-host] [also build test WARNING on linus/master v6.11-rc2 next-20240807] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/warp5tw-gmail-com/i2c-npcm-correct-the-read-write-operation-procedure/20240807-182210 base: https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git i2c/i2c-host patch link: https://lore.kernel.org/r/20240807100244.16872-6-kfting%40nuvoton.com patch subject: [PATCH v1 5/7] drivers: i2c: use i2c frequency table config: arm-randconfig-001-20240808 (https://download.01.org/0day-ci/archive/20240808/202408080319.de2B6PgU-lkp@xxxxxxxxx/config) compiler: arm-linux-gnueabi-gcc (GCC) 14.1.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240808/202408080319.de2B6PgU-lkp@xxxxxxxxx/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@xxxxxxxxx> | Closes: https://lore.kernel.org/oe-kbuild-all/202408080319.de2B6PgU-lkp@xxxxxxxxx/ All warnings (new ones prefixed by >>): drivers/i2c/busses/i2c-npcm7xx.c: In function 'npcm_i2c_init_clk': >> drivers/i2c/busses/i2c-npcm7xx.c:1926:14: warning: variable 'bus_freq_khz' set but not used [-Wunused-but-set-variable] 1926 | u32 bus_freq_khz; | ^~~~~~~~~~~~ >> drivers/i2c/busses/i2c-npcm7xx.c:1925:14: warning: variable 'src_clk_khz' set but not used [-Wunused-but-set-variable] 1925 | u32 src_clk_khz; | ^~~~~~~~~~~ vim +/bus_freq_khz +1926 drivers/i2c/busses/i2c-npcm7xx.c 56a1485b102ed1 Tali Perry 2020-05-27 1909 56a1485b102ed1 Tali Perry 2020-05-27 1910 /* 56a1485b102ed1 Tali Perry 2020-05-27 1911 * npcm_i2c_init_clk: init HW timing parameters. 0c47dd7d09bb5d Jonathan Neuschäfer 2022-01-29 1912 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB) 56a1485b102ed1 Tali Perry 2020-05-27 1913 * and bus frequency. 0c47dd7d09bb5d Jonathan Neuschäfer 2022-01-29 1914 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric. 0c47dd7d09bb5d Jonathan Neuschäfer 2022-01-29 1915 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended 56a1485b102ed1 Tali Perry 2020-05-27 1916 * by the HW designer, given core clock range (equations in comments below). 56a1485b102ed1 Tali Perry 2020-05-27 1917 * 56a1485b102ed1 Tali Perry 2020-05-27 1918 */ 56a1485b102ed1 Tali Perry 2020-05-27 1919 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) 56a1485b102ed1 Tali Perry 2020-05-27 1920 { a946fe9698f261 Tyrone Ting 2024-08-07 1921 struct SMB_TIMING_T *smb_timing; a946fe9698f261 Tyrone Ting 2024-08-07 1922 u8 scl_table_cnt = 0, table_size = 0; a946fe9698f261 Tyrone Ting 2024-08-07 1923 56a1485b102ed1 Tali Perry 2020-05-27 1924 u8 fast_mode = 0; 56a1485b102ed1 Tali Perry 2020-05-27 @1925 u32 src_clk_khz; 56a1485b102ed1 Tali Perry 2020-05-27 @1926 u32 bus_freq_khz; 56a1485b102ed1 Tali Perry 2020-05-27 1927 56a1485b102ed1 Tali Perry 2020-05-27 1928 src_clk_khz = bus->apb_clk / 1000; 56a1485b102ed1 Tali Perry 2020-05-27 1929 bus_freq_khz = bus_freq_hz / 1000; 56a1485b102ed1 Tali Perry 2020-05-27 1930 bus->bus_freq = bus_freq_hz; 56a1485b102ed1 Tali Perry 2020-05-27 1931 a946fe9698f261 Tyrone Ting 2024-08-07 1932 switch (bus_freq_hz) { a946fe9698f261 Tyrone Ting 2024-08-07 1933 case I2C_MAX_STANDARD_MODE_FREQ: a946fe9698f261 Tyrone Ting 2024-08-07 1934 smb_timing = SMB_TIMING_100KHZ; a946fe9698f261 Tyrone Ting 2024-08-07 1935 table_size = ARRAY_SIZE(SMB_TIMING_100KHZ); a946fe9698f261 Tyrone Ting 2024-08-07 1936 break; a946fe9698f261 Tyrone Ting 2024-08-07 1937 case I2C_MAX_FAST_MODE_FREQ: a946fe9698f261 Tyrone Ting 2024-08-07 1938 smb_timing = SMB_TIMING_400KHZ; a946fe9698f261 Tyrone Ting 2024-08-07 1939 table_size = ARRAY_SIZE(SMB_TIMING_400KHZ); 56a1485b102ed1 Tali Perry 2020-05-27 1940 fast_mode = I2CCTL3_400K_MODE; a946fe9698f261 Tyrone Ting 2024-08-07 1941 break; a946fe9698f261 Tyrone Ting 2024-08-07 1942 case I2C_MAX_FAST_MODE_PLUS_FREQ: a946fe9698f261 Tyrone Ting 2024-08-07 1943 smb_timing = SMB_TIMING_1000KHZ; a946fe9698f261 Tyrone Ting 2024-08-07 1944 table_size = ARRAY_SIZE(SMB_TIMING_1000KHZ); 56a1485b102ed1 Tali Perry 2020-05-27 1945 fast_mode = I2CCTL3_400K_MODE; a946fe9698f261 Tyrone Ting 2024-08-07 1946 break; a946fe9698f261 Tyrone Ting 2024-08-07 1947 default: 56a1485b102ed1 Tali Perry 2020-05-27 1948 return -EINVAL; 56a1485b102ed1 Tali Perry 2020-05-27 1949 } 56a1485b102ed1 Tali Perry 2020-05-27 1950 a946fe9698f261 Tyrone Ting 2024-08-07 1951 for (scl_table_cnt = 0 ; scl_table_cnt < table_size ; scl_table_cnt++) a946fe9698f261 Tyrone Ting 2024-08-07 1952 if (bus->apb_clk >= smb_timing[scl_table_cnt].core_clk) a946fe9698f261 Tyrone Ting 2024-08-07 1953 break; a946fe9698f261 Tyrone Ting 2024-08-07 1954 56a1485b102ed1 Tali Perry 2020-05-27 1955 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ a946fe9698f261 Tyrone Ting 2024-08-07 1956 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq & 0x7F), 56a1485b102ed1 Tali Perry 2020-05-27 1957 bus->reg + NPCM_I2CCTL2); 56a1485b102ed1 Tali Perry 2020-05-27 1958 56a1485b102ed1 Tali Perry 2020-05-27 1959 /* bits [8:7] are in I2CCTL3 reg */ a946fe9698f261 Tyrone Ting 2024-08-07 1960 iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_cnt].sclfrq >> 7) a946fe9698f261 Tyrone Ting 2024-08-07 1961 & 0x3), 56a1485b102ed1 Tali Perry 2020-05-27 1962 bus->reg + NPCM_I2CCTL3); 56a1485b102ed1 Tali Perry 2020-05-27 1963 56a1485b102ed1 Tali Perry 2020-05-27 1964 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ 56a1485b102ed1 Tali Perry 2020-05-27 1965 npcm_i2c_select_bank(bus, I2C_BANK_0); 56a1485b102ed1 Tali Perry 2020-05-27 1966 56a1485b102ed1 Tali Perry 2020-05-27 1967 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 56a1485b102ed1 Tali Perry 2020-05-27 1968 /* 56a1485b102ed1 Tali Perry 2020-05-27 1969 * Set SCL Low/High Time: 56a1485b102ed1 Tali Perry 2020-05-27 1970 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 56a1485b102ed1 Tali Perry 2020-05-27 1971 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 56a1485b102ed1 Tali Perry 2020-05-27 1972 */ a946fe9698f261 Tyrone Ting 2024-08-07 1973 iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT); a946fe9698f261 Tyrone Ting 2024-08-07 1974 iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT); 56a1485b102ed1 Tali Perry 2020-05-27 1975 a946fe9698f261 Tyrone Ting 2024-08-07 1976 iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5); 56a1485b102ed1 Tali Perry 2020-05-27 1977 } 56a1485b102ed1 Tali Perry 2020-05-27 1978 a946fe9698f261 Tyrone Ting 2024-08-07 1979 iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4); 56a1485b102ed1 Tali Perry 2020-05-27 1980 56a1485b102ed1 Tali Perry 2020-05-27 1981 /* Return to Bank 1, and stay there by default: */ 56a1485b102ed1 Tali Perry 2020-05-27 1982 npcm_i2c_select_bank(bus, I2C_BANK_1); 56a1485b102ed1 Tali Perry 2020-05-27 1983 56a1485b102ed1 Tali Perry 2020-05-27 1984 return 0; 56a1485b102ed1 Tali Perry 2020-05-27 1985 } 56a1485b102ed1 Tali Perry 2020-05-27 1986 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
