Hi Andi,
Sorry, I did not close on this one.
Anyway I will re-spin fixing the commit message issues. More comments inline below.
>-----Original Message-----
>From: Andi Shyti <andi.shyti@xxxxxxxxxx>
>Sent: Thursday, January 18, 2024 2:36 AM
>To: Boddu, Sai Pavan <sai.pavan.boddu@xxxxxxx>
>Cc: linux-kernel@xxxxxxxxxxxxxxx; linux-i2c@xxxxxxxxxxxxxxx; linux-arm-
>kernel@xxxxxxxxxxxxxxxxxxx; Simek, Michal <michal.simek@xxxxxxx>; Lars-
>Peter Clausen <lars@xxxxxxxxxx>; Wolfram Sang <wsa@xxxxxxxxxx>
>Subject: Re: [PATCH] i2c: cadence: Avoid fifo clear after start
>
>Hi,
>
>> >> b/drivers/i2c/busses/i2c-cadence.c
>> >> index de3f58b60dce..6f7d753a8197 100644
>> >> --- a/drivers/i2c/busses/i2c-cadence.c
>> >> +++ b/drivers/i2c/busses/i2c-cadence.c
>> >> @@ -633,6 +633,7 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id)
>> >>
>> >> if (hold_clear) {
>> >> ctrl_reg &= ~CDNS_I2C_CR_HOLD;
>> >> + ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
>> >
>> >I'm wondering whether the whole ctrl_reg should be reset after the first
>write.
>
>> [Boddu, Sai Pavan] previous implementation of read-modify-write was good
>then ?
>
>I don't know, I'm just asking... because rather than read-modify-write, this is
>read-modify-write-modify-write :-)
>
>I'm just wondering if after the first write ctrl_reg is still holding a valid value.
[Boddu, Sai Pavan] Yes, all bits in ctrl_reg stay as configured except CLR_FIFO which is self-clearing.
None of the other bits would change state.
CLR_FIFO post start of transactions should not be allowed; this patch address the same.
Regards,
Sai Pavan
>
>Andi
