Thomas Bonnefille wrote:
> Add nodes for the five I2C on the T-Head TH1520 RISCV SoC.
> All the I2C nodes are fed with the same clock named i2c_ic_clk.
> As there is currently no clock support, the i2c_ic_clk is exposed
> through a fixed-clock to mimic the existing nodes.
>
Thanks!
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
Tested-by: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@xxxxxxxxxxx>
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 66 +++++++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index d2fa25839012..86ae507576dc 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -153,6 +153,12 @@ sdhci_clk: sdhci-clock {
> #clock-cells = <0>;
> };
>
> + i2c_ic_clk: i2c-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <50000000>;
> + #clock-cells = <0>;
> + };
> +
> soc {
> compatible = "simple-bus";
> interrupt-parent = <&plic>;
> @@ -258,6 +264,36 @@ portc: gpio-controller@0 {
> };
> };
>
> + i2c0: i2c@ffe7f20000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xe7f20000 0x0 0x4000>;
> + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&i2c_ic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@ffe7f24000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xe7f24000 0x0 0x4000>;
> + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&i2c_ic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@ffe7f28000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xe7f28000 0x0 0x4000>;
> + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&i2c_ic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> gpio3: gpio@ffe7f38000 {
> compatible = "snps,dw-apb-gpio";
> reg = <0xff 0xe7f38000 0x0 0x1000>;
> @@ -312,6 +348,16 @@ portb: gpio-controller@0 {
> };
> };
>
> + i2c2: i2c@ffec00c000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xec00c000 0x0 0x4000>;
> + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&i2c_ic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> uart2: serial@ffec010000 {
> compatible = "snps,dw-apb-uart";
> reg = <0xff 0xec010000 0x0 0x4000>;
> @@ -322,6 +368,16 @@ uart2: serial@ffec010000 {
> status = "disabled";
> };
>
> + i2c3: i2c@ffec014000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xec014000 0x0 0x4000>;
> + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&i2c_ic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> dmac0: dma-controller@ffefc00000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0xff 0xefc00000 0x0 0x1000>;
> @@ -394,6 +450,16 @@ uart5: serial@fff7f0c000 {
> status = "disabled";
> };
>
> + i2c5: i2c@fff7f2c000 {
> + compatible = "thead,th1520-i2c", "snps,designware-i2c";
> + reg = <0xff 0xf7f2c000 0x0 0x4000>;
> + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&i2c_ic_clk>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> timer4: timer@ffffc33000 {
> compatible = "snps,dw-apb-timer";
> reg = <0xff 0xffc33000 0x0 0x14>;
> --
> 2.44.0
>
>
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