On 09/01/2024 13:58, Tudor Ambarus wrote: > GS101's Connectivity Peripheral blocks (peric0/1 blocks) which > include the I3C and USI (I2C, SPI, UART) only allow 32-bit > register accesses. > > Instead of specifying the reg-io-width = 4 everywhere, for each node, > the requirement should be deduced from the compatible. > > Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible. > Update the uart info name to be GS101 specific in order to > differentiate from the other exynos platforms. All the other settings > are not changed. > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
