On 10/12/23 13:57, Rob Herring wrote:
On Tue, Oct 10, 2023 at 09:09:25PM +0200, Marek Vasut wrote:
The ST M24C32-D behaves as a regular M24C32, except for the -D variant
which uses up another I2C address for Additional Write lockable page.
This page is 32 Bytes long and can contain additional data. Document
compatible string for it, so users can describe that page in DT. Note
that users still have to describe the main M24C32 area separately as
that is on separate I2C address from this page.
So 2 nodes for 1 device? Wouldn't it make more sense for the 1 node to
have 2 addresses?
It would, if the 32 Byte Additional Write lockable page was somehow
related to the main area, but it doesn't seem to be, except that they
are both on single chip.
