On Mon, Sep 11, 2023 at 04:07:49PM +0200, Yann Sionneau wrote: > The DesignWare IP can be synthesized with the IC_EMPTYFIFO_HOLD_MASTER_EN > parameter. > In this case, when the TX FIFO gets empty and the last command didn't have > the STOP bit (IC_DATA_CMD[9]), the controller will hold SCL low until > a new command is pushed into the TX FIFO or the transfer is aborted. > > When the controller is holding SCL low, it cannot be disabled. > The transfer must first be aborted. > Also, the bus recovery won't work because SCL is held low by the master. > > Check if the master is holding SCL low in __i2c_dw_disable() before trying > to disable the controller. If SCL is held low, an abort is initiated. > When the abort is done, then proceed with disabling the controller. > > This whole situation can happen for instance during SMBus read data block > if the slave just responds with "byte count == 0". > This puts the driver in an unrecoverable state, because the controller is > holding SCL low and the current __i2c_dw_disable() procedure is not > working. In this situation only a SoC reset can fix the i2c bus. > > Co-developed-by: Jonathan Borne <jborne@xxxxxxxxx> > Signed-off-by: Jonathan Borne <jborne@xxxxxxxxx> > Signed-off-by: Yann Sionneau <ysionneau@xxxxxxxxx> Applied to for-current, thanks!
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