On Wed, Sep 13, 2023 at 04:29:38PM -0700, Jan Bottorff wrote: > Errors were happening in the ISR that looked like corrupted > memory. This was because memory writes from the core enabling > interrupts were not yet visible to the core running the ISR. The > kernel log would get the message "i2c_designware APMC0D0F:00: > controller timed out" during in-band IPMI SSIF stress tests. > > Add a write barrier before enabling interrupts to assure data written > by the current core is visible to all cores before the interrupt fires. > > The ARM Barrier Litmus Tests and Cookbook has an example under > Sending Interrupts and Barriers that matches the usage in this > driver. That document says a DSB barrier is required. > > Signed-off-by: Jan Bottorff <janb@xxxxxxxxxxxxxxxxxxxxxx> > Reviewed-by: Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > Tested-by: Yann Sionneau <ysionneau@xxxxxxxxxxxxx> > --- Changelog? -- With Best Regards, Andy Shevchenko
