On Wed, Sep 13, 2023 at 11:04:00AM +0200, Yann Sionneau wrote: > On 13/09/2023 03:03, Jan Bottorff wrote: ... > > + /* > > + * To guarantee data written by the current core is visible to > > + * all cores, a write barrier is required. This needs to be > > + * before an interrupt causes execution on another core. > > + * For ARM processors, this needs to be a DSB barrier. > > + */ > > + wmb(); > > Apart from the commit message it looks good to me. > > If I understand correctly without this wmb() it is possible that the writes > to dev->msg_write_idx , dev->msg_read_idx = 0 etc would not yet be visible > to another CPU running the ISR handler right after enabling those. If this is the case, shouldn't we rather use READ_ONCE()/WRITE_ONCE() where appropriate? -- With Best Regards, Andy Shevchenko
