On Tue, Aug 22, 2023 at 06:51:37PM +0000, Vadim Pasternak wrote: > Add support for extended length of read and write transactions. > New FPGA logic allows to increase size of the read and write > transactions length. This feature is verified through capability > register 'CPBLTY_REG'. Two bits 5 and 6 of the register are used for > length capability detection. Value '10' indicates support of extended > transaction length - 128 bytes for read transactions and 132 for write > transactions. > > Signed-off-by: Vadim Pasternak <vadimp@xxxxxxxxxx> > Reviewed-by: Michael Shych <michaelsh@xxxxxxxxxx> Applied to for-next, thanks!
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