On Tue, Mar 14, 2023 at 10:26:56AM +0100, AngeloGioacchino Del Regno wrote:
> Il 14/03/23 02:18, Daniel Golle ha scritto:
> > Signed-off-by: Daniel Golle <daniel@xxxxxxxxxxxxxx>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index 43dd966d5ef5..54cabd366403 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible mt8168_compat = {
> > .max_dma_support = 33,
> > };
> > +static const struct mtk_i2c_compatible mt7981_compat = {
> > + .regs = mt_i2c_regs_v3,
>
> I've found a downstream kernel saying that MT7981 uses `mt_i2c_regs_v2`,
> hence the question:
>
> Are you sure that this is supposed to be v3?
Yes, I've seen that downstream kernel and it also patches
OFFSET_SLAVE_ADDR to be 0x94 instead of 0x4 (which is the only difference
between v2 and v3 regs).
So yes, I'm sure MT7981 and MT7988 use v3 register layout.
>
> Regards,
> Angelo
>
> > + .pmic_i2c = 0,
> > + .dcm = 0,
> > + .auto_restart = 1,
> > + .aux_len_reg = 1,
> > + .timing_adjust = 1,
> > + .dma_sync = 1,
> > + .ltiming_adjust = 1,
> > + .max_dma_support = 33
> > +};
> > +
> > static const struct mtk_i2c_compatible mt7986_compat = {
> > .quirks = &mt7622_i2c_quirks,
> > .regs = mt_i2c_regs_v1,
> > @@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c_of_match[] = {
> > { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
> > { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
> > { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
> > + { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat },
> > { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat },
> > { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat },
> > { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
>
>
