Il 06/03/23 14:47, Alexandre Mergnat ha scritto:
There are four I2C master channels in MT8365 with a same HW architecture.
Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
index 15ac4c1f0966..553c7516406a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -282,6 +282,45 @@ pwm: pwm@11006000 {
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
+ reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C0_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
You can compress the clocks to one single line, reaching 91 columns, on all of the
new i2c nodes that you're introducing. Please do that.
With that done:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
Regards,
Angelo
