On Sat, May 21, 2022 at 12:53:57PM +0200, Wolfram Sang wrote: > On Wed, Apr 27, 2022 at 01:19:10PM +0300, Mika Westerberg wrote: > > Before sending a MSI the hardware writes information pertinent to the > > interrupt cause to a memory location pointed by SMTICL register. This > > memory holds three double words where the least significant bit tells > > whether the interrupt cause of master/target/error is valid. The driver > > does not use this but we need to set it up because otherwise it will > > perform DMA write to the default address (0) and this will cause an > > IOMMU fault such as below: > > > > DMAR: DRHD: handling fault status reg 2 > > DMAR: [DMA Write] Request device [00:12.0] PASID ffffffff fault addr 0 > > [fault reason 05] PTE Write access is not set > > > > To prevent this from happening, provide a proper DMA buffer for this > > that then gets mapped by the IOMMU accordingly. > > > > Signed-off-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx> > > No maintainer response so far, but given this looks like an important > bugfix and you guys are all from Intel as well, I'll apply it this time. It's indeed. > Applied to for-current, thanks! Thanks, Wolfram! -- With Best Regards, Andy Shevchenko
