On Tue, 8 Feb 2022 17:03:09 -0600, Terry Bowman wrote: > On 2/8/22 15:46, Jean Delvare wrote: > > If so, while there's indeed nothing to be done for the most recent > > systems where only MMIO access is possible, you may still need to > > enable MMIO access through legacy I/O if you try to use MMIO on > > chipsets where both are possible. I'm not sure what exactly where you > > set the limit. In the last patch you say that 0x51 is the first > > revision of the family 17h CPUs, but is family 17h the first where MMIO > > is available, or the first where legacy I/O isn't? > > Family 17h, SMBus PCI ID >= 0x51 is the first where cd6h/cd7h port I/O is disabled. > If SMBus PCI ID < 0x51 then cd6h/cd7h port I/O is used. OK, we are safe then :-) -- Jean Delvare SUSE L3 Support
