On Wed, Mar 10, 2021 at 03:51:45PM +0100, Jean Delvare wrote:
> On Mon, 8 Mar 2021 14:20:20 +0200, Andy Shevchenko wrote:
...
> > - res->end = res->start + 3;
> > - res->flags = IORESOURCE_MEM;
> > + res->start += SBREG_SMBCTRL;
>
> I can't see why you no longer set res->end and res->flags here. I can
> imagine that pci_p2sb_bar() may have set the flags for us, but not that
> ->end is still correct after you fixed up ->start. Am I missing
> something?
Good catch of the res->end! But flags actually may be MEM64, which the
original code doesn't properly handle.
...
> > static const struct x86_cpu_id p2sb_cpu_ids[] = {
> > X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, PCI_DEVFN(13, 0)),
> > + X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, PCI_DEVFN(31, 1)),
> > + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, PCI_DEVFN(31, 1)),
> > + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, PCI_DEVFN(31, 1)),
> > + X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, PCI_DEVFN(31, 1)),
> > + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, PCI_DEVFN(31, 1)),
> > + X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, PCI_DEVFN(31, 1)),
> > {}
> > };
>
> Any reason why this is added in this patch instead of [3/7] (PCI: New
> Primary to Sideband (P2SB) bridge support library)?
Filling this on demand, no user no entry. I think it's how we assume the code
to be applied in the kernel.
--
With Best Regards,
Andy Shevchenko
