On Tue, 2021-12-07 at 17:21 +1300, Chris Packham wrote: > Can you give this a test on your setup. I've tried it on the setup > where I had the original problem that led to 4a8ac5e45cda and it > seems OK so far (I'll leave my test running overnight). Tested-by: Maxime Bizon <mbizon@xxxxxxxxxx> Small reservation though, it does not seem to be understood why this polling is needed. Reading the driver history, the theory is that the controller will trigger an interrupt at the end of transfer just after the last SCL cycle, but irrespective of whether SCL goes high, which happens if a slave "stretch" the clock until it's ready to answer. Supposedly when that happen, CSR_MCF bit would be 0 at interrupt time, meaning bus is busy, and we have to poll until it goes to 1 meaning the slave has released SCL. I have no slave that does clock stretching on my board so I cannot test the theory. On my mpc8347 device, i2c clock speed set to 90kHz, I've never seen a case where MCR was 0 at interrupt time. For i2c experts here, is 100us enough in that case ? I could not any maximum stretch time in i2c specification. My CPU user manual is IMO vague on this precise topic, hopefully an NXP knowledgeable employee will read this and enlighten us. Thanks, -- Maxime
