On 2/07/21 3:27 pm, Chris Packham wrote:
> Prior to commit 1538d82f4647 ("i2c: mpc: Interrupt driven transfer") the
> old interrupt handler would reread MPC_I2C_SR after checking the CSR_MIF
> bit. When the driver was re-written this was removed as it seemed
> unnecessary. However as it turns out this is necessary for i2c devices
> which do clock stretching otherwise we end up thinking the bus is still
> busy when processing the interrupt.
>
> Fixes: 1538d82f4647 ("i2c: mpc: Interrupt driven transfer")
> Signed-off-by: Chris Packham <chris.packham@xxxxxxxxxxxxxxxxxxx>
Just a heads up that this hasn't totally fixed the issue. Just made it
less likely to occur. I'm now wondering if we should be treating MCF as
a busy bit and waiting for it to clear (with approrpriate timeouts)
instead of just flagging an error immediately.
> ---
> drivers/i2c/busses/i2c-mpc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
> index dcca9c2396db..6d5014ebaab5 100644
> --- a/drivers/i2c/busses/i2c-mpc.c
> +++ b/drivers/i2c/busses/i2c-mpc.c
> @@ -635,6 +635,8 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
>
> status = readb(i2c->base + MPC_I2C_SR);
> if (status & CSR_MIF) {
> + /* Read again to allow register to stabilise */
> + status = readb(i2c->base + MPC_I2C_SR);
> writeb(0, i2c->base + MPC_I2C_SR);
> mpc_i2c_do_intr(i2c, status);
> return IRQ_HANDLED;
